In recent years, worldwide demand for wireless cellular communications has increased dramatically. Radiotelephones manufactured to meet this burgeoning demand must adhere to standards such as the Global System for Mobile Communications (GSM) standard. Another standard, the Digital Cellular System (DCS) standard, is based on GSM, but is directed towards higher cell density and lower power. A third standard, Personal Communications Services (PCS) is a “catch all” for many digital cellular systems, including GSM, operating in North America. These standards all require precise output power control over a large dynamic range in order to prevent a transmitter located in one cell from interfering with the reception of transmissions from other transmitters in neighboring cells.
A key component common to all radiotelephones is a radio frequency (RF) power amplifier (PA). In modern digital radiotelephones, PAs receive as input a modulated RF carrier. The radio frequency carrier is what “carries” digital information such as digitized voice or data to a cellular base station. Before reaching the PA, the RF carrier is too weak to be received by a cellular base station. Therefore, it is the function of the PA to boost the power of the RF carrier to a level sufficient for reception by a cellular base station.
In GSM radiotelephones, the adjustable power control signal must comply with a specification known as a “burst mask.” The burst mask specifies the rise time, fall time, duration, and power levels associated with the adjustable power control signal. The GSM signal consists of eight equal time slots. Each time slot must conform to the burst mask specification. The output of an integrator circuit may be used to control the ramp-up time and ramp-down time of a PA control signal that is responsive to an input ramp signal VRAMP (FIG. 1). The amplitude of the input ramp signal VRAMP dictates that the output power of the PA must conform to the shape of the burst mask.
A problem manifests itself in the prior art due to undesirable switching transients that occur when the up and down ramp of the burst is not smooth or changes shape nonlinearly. These switching transients also occur if the control slope of the power amplifier has an inflection point within the output range, or if the control slope is very steep. In particular, this problem will occur when the integrator circuit output attempts to drive the PA beyond its maximum output power capability, which results in saturation of the PA.
FIG. 1 shows a PA integration loop 10 according to the prior art. The PA integration loop 10 includes an integrator 12, PA circuitry 14, and detector circuitry 16. The integrator 12 includes an integrator differential amplifier 18, such as an operational amplifier, a first resistive element R1, a second resistive element R2, a first capacitive element C1, and a second capacitive element C2. One end of the first resistive element R1 is coupled to a non-inverting input to the integrator differential amplifier 18 and an opposite end of the first resistive element R1 receives the input ramp signal VRAMP. The first capacitive element C1 is coupled between the non-inverting input to the integrator differential amplifier 18 and ground. As such, the first resistive element R1 and the first capacitive element C1 form a lowpass filter to filter the input ramp signal VRAMP to provide a filtered signal to the integrator differential amplifier 18. The second resistive element R2 is coupled between an inverting input to the integrator differential amplifier 18 and a detection output from the detector circuitry 16. The second capacitive element C2 is coupled between the inverting input and an output from the integrator differential amplifier 18. The detection output from the detector circuitry 16 provides a detector output signal VDET and the output from the integrator differential amplifier 18 provides an integrator output signal IOUT to the PA circuitry 14.
The PA circuitry 14 receives and amplifies an RF input signal RFIN to provide an RF output signal RFOUT having a PA output voltage. The detector circuitry 16 receives and forwards the RF output signal RFOUT to other circuitry (not shown) and detects the PA output voltage to provide the detector output signal VDET, which is indicative of the PA output voltage. The PA output voltage is controlled by the PA circuitry 14 in response to the integrator output signal IOUT. The PA output voltage may directly follow the integrator output signal IOUT. In summary, the integrator 12 receives and integrates the detector output signal VDET to provide the integrator output signal IOUT based on a setpoint established by the input ramp signal VRAMP, the PA circuitry 14 receives and amplifies the RF input signal RFIN to provide the RF output signal RFOUT in response to the integrator output signal IOUT, and the detector circuitry 16 detects the PA output voltage of the RF output signal RFOUT to provide the detector output signal VDET. As such, the PA integration loop 10 may function to minimize a difference between a desired PA output voltage, as represented by the input ramp signal VRAMP, and a detected PA output voltage, as represented by the detector output signal VDET.
In this regard, the integrator 12 operates to drive the difference between the desired PA output voltage and the detected PA output voltage to zero by integrating differences between these two voltages over time. Therefore, the integrator output signal IOUT increases over time as long as the difference between the two voltages persists. However, when the PA circuitry 14 is driven into saturation, which can occur when the desired PA output voltage is beyond the capability of the PA circuitry 14 to provide such a voltage, a difference between the desired PA output voltage and the detected PA output voltage persists, thereby resulting in the integrator 12 continuing to drive the integrator output signal IOUT toward a maximum possible voltage level such as a power supply voltage, while the output power of the PA circuitry 14 remains at a saturated level, as illustrated in FIG. 2.
When the burst is completed, the input ramp signal VRAMP needs to ramp down. However, the integrator output signal IOUT will have to first fall from the maximum possible voltage level, as illustrated in FIG. 3. During the time it takes for the integrator output signal IOUT to begin to fall, the PA output power will not immediately follow the input ramp signal VRAMP down. However, once the input ramp signal VRAMP decreases to a voltage level in which the PA circuitry 14 is once again controllable, the integrator output signal IOUT must “catch up” with the input ramp signal VRAMP. As a result, there will be a sharp drop in the PA's output power, as shown in FIG. 4. As illustrated in FIG. 5, this sharp drop in the PA's output power typically results in failure of the European Telecommunications Standards Institute (ETSI) switching spectrum specification. Notice that both the −400 kHz signal and the +400 kHz signal exceed the ETSI limit as the input ramp signal VRAMP descends.
Thus, there remains a need to provide a circuit and methodology for controlling the saturation levels of power amplifiers to prevent switching transients and maintain desirable switching spectrums for the power amplifiers' outputs.